A problem for parallel, distributed systems is how to assign and manage memory resources. Memory is typically attached to a host processor using a shared bus where appropriate protocols are applied to enable coherency and consistency. In this strategy memory controller hardware on the processor core can observe the traffic on the common bus, then update or invalidate cache lines to reflect the operations performed by the other processors. A many-node multiprocessor system may also use “directory-based” coherence techniques to allow processor nodes to see memory traffic that relates to pages or cache lines on which they are working. These strategies become increasingly performance hampering and improvements in distributed systems are needed.
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